In synchronous circuits data is typically latched into memory elements by one or more globally distributed clock signals. The generation of the clock signals and their distribution to the memory elements must adhere to strict requirements to avoid circuit malfunction. In synchronous circuits the clock signal is coupled to all of the registers, flip-flops, and latches as well as to dynamic gates. This large fan-out causes significant delays in the clock signal distribution. It is imperative that the clock signal provided to the logic elements be precisely aligned.
Synchronous inputs to a system obey strict timing relations governed by the system clock. For example, a synchronous input to a flip-flop changes only within a predetermined part of the system clock period. The predetermined timing window for the change in the input is defined to ensure that the setup and hold time requirements of the flip-flop are satisfied. The setup time defines the amount of time that a data input must be available and stable before an active clock edge. The hold time describes the length of time that the data to be clocked into the flip-flop must remain available and stable after an active clock edge.
A delay in the clock signal to a logic gate can violate these timing requirements which can put the circuit into a metastable state which is where the circuit may linger or oscillate indefinitely between two stable states. Failures resulting from metastable behavior are particularly troublesome and mysterious because they are intermittent, random, and virtually untraceable. Larger clock delays can cause the gate to not have switched the current clock cycle value to the output when the output is sampled by a subsequent logic gate.
In multiple chip systems the system clock must be aligned at the point of clock pulse delivery to the logic that is at the end of the clock distribution tree of each of the chips. The clock distribution tree delay for a chip varies due to differences in the chip manufacturing process parameters as well as different clock designs. Process variations between two chips from the same wafer can be significant, process variations between chips from different wafers are typically even larger and chips of different design may be very different. As a result, the clock distribution delay within a system depends on the individual chips that are placed in the system. To take into account the effect of process variations and different chips designs on clock delay, the clock distribution delays in multiple chip systems are calibrated after the chips have been mounted in a system. For example, in systems prior to this invention either a clock control chip or each chip may include a programmable delay. The delay for a chip can be adjusted by providing a delay value to an input which determines how many units of delay are to be included in the clock distribution tree so as to align the clock signal at the end of each clock distribution tree throughout the multiple chip system. This calibration process can be a complicated and time consuming additional step in the manufacturing process which increases the product cost. Furthermore, when a chip is replaced in the system, differences in the clock delay of the replacement chip compared to the replaced chip can destroy the clock alignment, thereby limiting the repairability of the system.
Thus an improved clock distribution system that overcomes these and other problems of the prior art would be highly desirable.